A 125 MHz Digital Equalizer for Broadband Communications

A 125 MHz digital equalizer has been designed based on a 0.25 μm CMOS standard cell library. Partially conforming to the Gigabit Ethernet 1000Base-T standard, the equalizer includes a 16-tap feed-forward adaptive FIR filters accepting 8-bit input, and a 16-tap decision-feedback adaptive FIR filters producing 5-level output symbols. The modified Booth encoding and Wallace tree compression schemes are applied in the multiplication and summation for convolution computation. The timing constraint around the decision-feedback path is mitigated by using the architecture of parallel processing with symbol lookahead. The chip area is 1 37 1 37 mm2. The worst-case critical-path delay is 6.75 nsec. The power dissipation is 460 mW operating under a 2.5 V supply. Index Terms — Adaptive equalizer, FIR filters, Gigabit Ethernet.